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FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 11 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DAC
1994
ACM
15 years 10 months ago
Rectilinear Steiner Trees with Minimum Elmore Delay
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...
ASPDAC
2001
ACM
103views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Efficient minimum spanning tree construction without Delaunay triangulation
Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs o...
Hai Zhou, Narendra V. Shenoy, William Nicholls
CAIP
2009
Springer
114views Image Analysis» more  CAIP 2009»
15 years 10 months ago
Decision Trees Using the Minimum Entropy-of-Error Principle
Binary decision trees based on univariate splits have traditionally employed so-called impurity functions as a means of searching for the best node splits. Such functions use estim...
Joaquim Marques de Sá, João Gama, Ra...
DAC
2005
ACM
15 years 8 months ago
Minimizing peak current via opposite-phase clock tree
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu