4507 search results - page 591 / 902 » Generalized Binet dynamics |
153
click to vote
FPGA
2009
ACM
16 years 1 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
162
click to vote
ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
172
click to vote
CEC
2009
IEEE
16 years 1 months ago
2009
IEEE
— Reservoir modeling is an on-going activity during the production life of a reservoir. One challenge to constructing accurate reservoir models is the time required to carry out ...
158
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Networks-on-chip (NoC) for general-purpose multiprocessors require quality of service mechanisms to allow realtime streaming applications to be executed along with laten...
169
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...