Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
In many text-processing applications, we would like shapes that expand (or shrink) in size to fit their textual content. We address how to efficiently compute the minimum size fo...
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
In this paper we present a novel system for monitoring a computer user’s posture and activities in front of the computer (e.g., reading, speaking on the phone, etc.) for self-re...