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GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
16 years 10 days ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
16 years 10 days ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
DAC
2003
ACM
16 years 9 days ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
DOCENG
2003
ACM
16 years 9 days ago
Extending xQuery with transformation operators
In this paper, we propose to extend XQuery - the XML query language - with a set of transformation operators which will produce a copy of an XML tree in which some subtrees will b...
Emmanuel Bruno, Jacques Le Maitre, Elisabeth Muris...
DOCENG
2003
ACM
16 years 9 days ago
Accuracy improvement of automatic text classification based on feature transformation
In this paper, we describe a comparative study on techniques of feature transformation and classification to improve the accuracy of automatic text classification. The normalizati...
Guowei Zu, Wataru Ohyama, Tetsushi Wakabayashi, Fu...