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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 11 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 11 months ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 11 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
APSEC
2002
IEEE
15 years 11 months ago
A Predictive Performance Model to Evaluate the Contention Cost in Application Servers
In multi-tier enterprise systems, application servers are key components to implement business logic and provide services. To support a large number of simultaneous accesses from ...
Shiping Chen, Ian Gorton
ISMVL
2002
IEEE
113views Hardware» more  ISMVL 2002»
15 years 11 months ago
On the Construction of Multiple-Valued Decision Diagrams
Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider ways to improve the construction of multiple-value...
D. Michael Miller, Rolf Drechsler