3119 search results - page 466 / 624 » General Default Logic |
138
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequat...
160
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
172
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
173
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
162
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...