3119 search results - page 463 / 624 » General Default Logic |
140
click to vote
DAC
2008
ACM
16 years 7 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
178
click to vote
DAC
2008
ACM
16 years 7 months ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
161
click to vote
DAC
2008
ACM
16 years 7 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
150
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
161
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...