3119 search results - page 376 / 624 » General Default Logic |
145
click to vote
DAC
2008
ACM
16 years 7 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
135
click to vote
DAC
2002
ACM
16 years 7 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
164
click to vote
DAC
2002
ACM
16 years 7 months ago
2002
ACM
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
155
click to vote
DAC
2003
ACM
16 years 7 months ago
2003
ACM
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
138
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...