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TCAD
1998
127views more  TCAD 1998»
15 years 6 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
AND
2010
15 years 4 months ago
Document: a useful level for facing noisy data
In this paper we will present a set of experiments using large digitalized collections of books to show that logical structures can be extracted with good quality when working at ...
Hervé Déjean, Jean-Luc Meunier
168
Voted
DAC
2012
ACM
13 years 9 months ago
Improving gate-level simulation accuracy when unknowns exist
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
Kai-Hui Chang, Chris Browy
DAC
2005
ACM
16 years 7 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
POPL
2007
ACM
16 years 7 months ago
Semantics of static pointcuts in aspectJ
In aspect-oriented programming, one can intercept events by writing patterns called pointcuts. The pointcut language of the most popular aspect-oriented programming language, Aspe...
Pavel Avgustinov, Elnar Hajiyev, Neil Ongkingco, O...