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DAC
2007
ACM
16 years 7 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2005
ACM
15 years 8 months ago
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Finding all satisfying assignments of a propositional formula has many applications in the design of hardware and software. An approach to this problem augments a clause-recording...
HoonSang Jin, Fabio Somenzi
GLVLSI
2011
IEEE
351views VLSI» more  GLVLSI 2011»
14 years 10 months ago
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
16 years 17 days ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
16 years 21 days ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...