1862 search results - page 202 / 373 » General Architecture for Hardware Implementation of Genetic ... |
177
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DAC
2003
ACM
15 years 11 months ago
2003
ACM
A new methodology is presented to solve a strongly nonlinear circuit, characterized by Piece-Wise Linear (PWL) functions, symbolically and explicitly in terms of its circuit param...
200
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ISSS
1995
IEEE
15 years 10 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
183
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ISCA
2010
IEEE
15 years 8 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
145
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ISLPED
1997
ACM
15 years 10 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
162
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...