Sciweavers

1862 search results - page 146 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
GI
1998
Springer
15 years 10 months ago
Self-Organizing Data Mining
"KnowledgeMiner" was designed to support the knowledge extraction process on a highly automated level. Implemented are 3 different GMDH-type self-organizing modeling algo...
Frank Lemke, Johann-Adolf Müller
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
14 years 9 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
16 years 14 days ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
15 years 6 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
DAC
2003
ACM
16 years 7 months ago
Optimal integer delay budgeting on directed acyclic graphs
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...