Sciweavers

1862 search results - page 145 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
PLDI
1994
ACM
15 years 10 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
16 years 25 days ago
Adaptive delay compensation in multi-dithering adaptive control
Abstract— Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was present...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
BMCBI
2004
112views more  BMCBI 2004»
15 years 6 months ago
A double classification tree search algorithm for index SNP selection
Background: In population-based studies, it is generally recognized that single nucleotide polymorphism (SNP) markers are not independent. Rather, they are carried by haplotypes, ...
Peisen Zhang, Huitao Sheng, Ryuhei Uehara
GECCO
2009
Springer
258views Optimization» more  GECCO 2009»
15 years 11 months ago
Evolutionary learning of local descriptor operators for object recognition
Nowadays, object recognition is widely studied under the paradigm of matching local features. This work describes a genetic programming methodology that synthesizes mathematical e...
Cynthia B. Pérez, Gustavo Olague
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 13 days ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood