Sciweavers

1862 search results - page 120 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
APCCAS
2006
IEEE
261views Hardware» more  APCCAS 2006»
15 years 8 months ago
A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs
- In this paper, the grouped scheme is specially applied to compute the fast Fourier transform (FFT) when the portions of transformed outputs are calculated selectively. The groupe...
Chih-Peng Fan, Guo-An Su
ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
16 years 3 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
16 years 1 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
16 years 1 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
CHES
2001
Springer
124views Cryptology» more  CHES 2001»
15 years 11 months ago
High-Radix Design of a Scalable Modular Multiplier
This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and t...
Alexandre F. Tenca, Georgi Todorov, Çetin K...