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IPPS
2006
IEEE
15 years 12 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
IPPS
2006
IEEE
15 years 12 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
WSCG
2001
97views more  WSCG 2001»
15 years 7 months ago
Parallel Ray Tracing with 5D Adaptive Subdivision
We present strategies for parallelising ray tracing based on 5D adaptive subdivision. Our goals are to obtain good speed-up and to efficiently balance the load between the process...
G. Simiakakis, Theoharis Theoharis, A. M. Day
185
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ICPP
2000
IEEE
15 years 10 months ago
Nonblocking WDM Multicast Switching Networks
ÐWith ever increasing demands on bandwidth from emerging bandwidth-intensive applications, such as video conferencing, E-commerce, and video-on-demand services, there has been an ...
Yuanyuan Yang, Jianchao Wang, Chunming Qiao
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
16 years 2 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...