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» Gate Sizing Using a Statistical Delay Model
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182
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DC
2010
15 years 6 months ago
Model checking transactional memories
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memo...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
ISCAS
2006
IEEE
118views Hardware» more  ISCAS 2006»
15 years 12 months ago
A robust continuous-time multi-dithering technique for laser communications using adaptive optics
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
16 years 6 months ago
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasma...
BROADNETS
2007
IEEE
16 years 8 days ago
TCP dynamics over IEEE 802.11E WLANs: Modeling and throughput enhancement
— Today, IEEE 802.11 Wireless LAN (WLAN) has become a prevailing solution for broadband wireless Internet access while Transport Control Protocol (TCP) is the dominant transport ...
Jeonggyun Yu, Sunghyun Choi, Daji Qiao
188
Voted
TVLSI
2010
15 years 18 days ago
Asynchronous Current Mode Serial Communication
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam ...