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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
16 years 22 days ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
16 years 1 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...
SBCCI
2009
ACM
187views VLSI» more  SBCCI 2009»
15 years 11 months ago
Design of low complexity digital FIR filters
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
Levent Aksoy, Diego Jaccottet, Eduardo Costa
DAC
2003
ACM
15 years 11 months ago
Dos and don'ts of CTL state coverage estimation
Coverage estimation for model checking quantifies the completeness of a set of properties. We present an improved version of the algorithm of Hoskote et al. [7] that applies to a...
Nikhil Jayakumar, Mitra Purandare, Fabio Somenzi
DAC
1996
ACM
15 years 10 months ago
Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing
Hot-carrier eects and electromigration are the two important failure mechanisms that signi cantly impact the long-term reliability of high-density VLSI ICs. In this paper, we prese...
Aurobindo Dasgupta, Ramesh Karri