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DAC
2005
ACM
16 years 7 months ago
Effective bounding techniques for solving unate and binate covering problems
Covering problems arise in many areas of electronic design automation such as logic minimization and technology mapping. An exact solution can critically impact both size and perf...
Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
FAABS
2004
Springer
15 years 11 months ago
Towards Timed Automata and Multi-agent Systems
Abstract. The design of reactive systems must comply with logical correctness (the system does what it is supposed to do) and timeliness (the system has to satisfy a set of tempora...
Guillaume Hutzler, Hanna Klaudel, D. Yue Wang
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
15 years 11 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
DAC
2000
ACM
16 years 7 months ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang
DAC
2005
ACM
16 years 7 months ago
IODINE: a tool to automatically infer dynamic invariants for hardware designs
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
Sudheendra Hangal, Naveen Chandra, Sridhar Narayan...