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» Fuzzy logic in architectural design
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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 11 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 11 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
DAC
2006
ACM
16 years 7 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
AIIDE
2008
15 years 8 months ago
Recombinable Game Mechanics for Automated Design Support
Systems that provide automated game-design support-whether fully automated game generators, or tools to assist human designers--must be able to maintain a representation of a game...
Mark J. Nelson, Michael Mateas
IWPSE
2003
IEEE
15 years 11 months ago
CVS Release History Data for Detecting Logical Couplings
The dependencies and interrelations between classes and modules affect the maintainability of object-oriented systems. It is therefore important to capture weaknesses of the softw...
Harald Gall, Mehdi Jazayeri, Jacek Krajewski