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ASPDAC
2001
ACM
86views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication
Abstract-- We are proposing "PPRAM-Link": a new highspeed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logic...
Takanori Okuma, Koji Hashimoto, Kazuaki Murakami
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
15 years 10 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ETFA
2005
IEEE
15 years 12 months ago
Assessment of PROFIBUS networks using a fault injection framework
Industrial control systems architectures have been evolving to the decentralization of control tasks. This evolution associated with the time-critical nature of these tasks, incre...
J. A. Carvalho, A. S. Carvalho, Paulo Portugal
IPPS
2003
IEEE
15 years 11 months ago
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Dennis Abts, Steve Scott, David J. Lilja