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ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
15 years 10 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
FROCOS
2007
Springer
15 years 10 months ago
Certification of Automated Termination Proofs
Abstract. Nowadays, formal methods rely on tools of different kinds: proof assistants with which the user interacts to discover a proof step by step; and fully automated tools whic...
Evelyne Contejean, Pierre Courtieu, Julien Forest,...
HOTNETS
2010
15 years 1 months ago
Next generation on-chip networks: what kind of congestion control do we need?
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting core differences between NoCs and traditional networks. As an in...
George Nychis, Chris Fallin, Thomas Moscibroda, On...
LCTRTS
2007
Springer
16 years 17 days ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...
DEBS
2009
ACM
16 years 29 days ago
Distributed complex event processing with query rewriting
The nature of data in enterprises and on the Internet is changing. Data used to be stored in a database first and queried later. Today timely processing of new data, represented ...
Nicholas Poul Schultz-Møller, Matteo Miglia...