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HPCA
2005
IEEE
16 years 12 hour ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
BROADNETS
2007
IEEE
16 years 22 days ago
Modeling and performance analysis of an improved DCF-based mechanism under noisy channel
The ISM free-licence band is highly used by wireless technologies such IEEE 802.11, Bluetooth as well as private wireless schemes. This huge utilisation increases dramatically the ...
Adlen Ksentini, Marc Ibrahim
ISCAS
2008
IEEE
110views Hardware» more  ISCAS 2008»
16 years 24 days ago
Non-traditional irregular interconnects for massive scale SoC
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
Christof Teuscher, Anders A. Hansson
ANCS
2008
ACM
15 years 8 months ago
Performing time-sensitive network experiments
Time-sensitive network experiments are difficult. There are major challenges involved in generating high volumes of sufficiently realistic traffic. Additionally, accurately measur...
Neda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick...
ECCV
2006
Springer
16 years 8 months ago
Comparison of Energy Minimization Algorithms for Highly Connected Graphs
Algorithms for discrete energy minimization play a fundamental role for low-level vision. Known techniques include graph cuts, belief propagation (BP) and recently introduced tree-...
Vladimir Kolmogorov, Carsten Rother