2291 search results - page 235 / 459 » Future Graphics Architectures |
151
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IISWC
2009
IEEE
16 years 1 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
159
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
154
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EUROPAR
2009
Springer
16 years 1 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
179
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IPPS
2007
IEEE
16 years 27 days ago
2007
IEEE
The integration of clusters of computers into computational grids has recently gained the attention of many computational scientists. While considerable progress has been made in ...
161
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NOCS
2007
IEEE
16 years 27 days ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...