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PDPTA
2000
15 years 7 months ago
An Economy Driven Resource Management Architecture for Global Computational Power Grids
The growing computational power requirements of grand challenge applications has promoted the need for linking highperformance computational resources distributed across multiple ...
Rajkumar Buyya, David Abramson, Jonathan Giddy
HPCA
2009
IEEE
16 years 7 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
HPCA
2007
IEEE
16 years 6 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
16 years 15 days ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
16 years 3 days ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri