In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
The Experimentation Command and Control Interface (XC2I) project has developed an architecture for a Webservice based viewer/controller for use with distributed simulations suppor...
Katherine L. Morse, Ryan Brunton, J. Mark Pullen, ...
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...