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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 11 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
15 years 11 months ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
DSRT
2004
IEEE
15 years 10 months ago
An Architecture for Web-Services Based Interest Management in Real Time Distributed Simulation
The Experimentation Command and Control Interface (XC2I) project has developed an architecture for a Webservice based viewer/controller for use with distributed simulations suppor...
Katherine L. Morse, Ryan Brunton, J. Mark Pullen, ...
ICS
2000
Tsinghua U.
15 years 10 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
CGF
2010
105views more  CGF 2010»
15 years 6 months ago
Streaming-Enabled Parallel Dataflow Architecture for Multicore Systems
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...