17967 search results - page 414 / 3594 » Functional timing optimization |
147
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ICPR
2008
IEEE
16 years 1 months ago
2008
IEEE
In the paper we propose a novel multi-layer Mixed Markov model for detecting relevant changes in registered aerial images taken with significant time differences. The introduced ...
168
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DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
Due to fast technology scaling, negative bias temperature instability (NBTI) has become a major reliability concern in designing modern integrated circuits. In this paper, we prese...
166
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ASYNC
2002
IEEE
15 years 11 months ago
2002
IEEE
We demonstrate how 1-of-n encoded speed-independent circuits provide a good framework for constructing smart card functions that are resistant to side channel attacks and fault in...
162
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
198
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RTAS
2000
IEEE
15 years 11 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...