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MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
15 years 5 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
MBEES
2010
15 years 4 months ago
Test Case Integration: From Components to Systems
In a component-based development approach system integration generally implies the packaging and deployment of a group of software components on hardware units, possibly hiding th...
Bernhard Schätz, Christian Pfaller
DAC
2000
ACM
15 years 10 months ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya
BMCBI
2006
102views more  BMCBI 2006»
15 years 6 months ago
Taking U out, with two nucleases?
Background: REX1 and REX2 are protein components of the RNA editing complex (the editosome) and function as exouridylylases. The exact roles of REX1 and REX2 in the editosome are ...
I. Saira Mian, Elizabeth A. Worthey, Reza Salavati
CASES
2003
ACM
15 years 11 months ago
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
Ramnath Venugopalan, Prasanth Ganesan, Pushkin Ped...