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DATE
2004
IEEE
123views Hardware» more  DATE 2004»
15 years 10 months ago
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currentl...
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
GECCO
2010
Springer
191views Optimization» more  GECCO 2010»
15 years 6 months ago
Fitness importance for online evolution
To complement standard fitness functions, we propose "Fitness Importance" (FI) as a novel meta-heuristic for online learning systems. We define FI and show how it can be...
Philip Valencia, Raja Jurdak, Peter Lindsay
CGF
2005
101views more  CGF 2005»
15 years 6 months ago
Modeling Color Properties of Tiled Displays
The concept of tiled displays can be successful only if such displays are made to look like a single display perceptually. The two issues that need to be solved to achieve this go...
Aditi Majumder, M. Gopi
CSREAESA
2010
15 years 4 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
ITC
2003
IEEE
157views Hardware» more  ITC 2003»
15 years 12 months ago
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurren...
Ramesh Karri, Grigori Kuznetsov, Michael Göss...