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ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
16 years 23 days ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
183
Voted
NETWORKS
2008
15 years 6 months ago
Lagrangian relaxation and enumeration for solving constrained shortest-path problems
Recently published research indicates that a vertex-labeling algorithm based on dynamic-programming concepts is the most efficient procedure available for solving constrained shor...
W. Matthew Carlyle, Johannes O. Royset, R. Kevin W...
ACCV
2009
Springer
16 years 1 months ago
Planar Scene Modeling from Quasiconvex Subproblems
In this paper, we propose a convex optimization based approach for piecewise planar reconstruction. We show that the task of reconstructing a piecewise planar environment can be se...
Visesh Chari, Anil Kumar Nelakanti, Chetan Jakkoju...
BMVC
2001
15 years 9 months ago
Robust Registration of 2D and 3D Point Sets
This paper introduces a new method of registering point sets. The registration error is directly minimized using general-purpose non-linear optimization (the Levenberg–Marquardt...
Andrew W. Fitzgibbon
ICASSP
2011
IEEE
14 years 10 months ago
Computing the nonnegative 3-way tensor factorization using Tikhonov regularization
This paper deals with the minimum polyadic decomposition of a nonnegative three-way array. The main advantage of the nonnegativity constraint is that the approximation problem bec...
Jean-Philip Royer, Pierre Comon, Nadège Thi...