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ASPDAC
2008
ACM
90views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Vertical via design techniques for multi-layered P/G networks
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...
Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ATAL
2008
Springer
15 years 8 months ago
The effects of market-making on price dynamics
This paper studies price properties in continuous double-auction markets in the presence of marketmakers, agents with special responsibilities for maintaining liquidity and orderl...
Sanmay Das
CF
2005
ACM
15 years 8 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
CHI
2005
ACM
15 years 8 months ago
Improving revisitation in fisheye views with visit wear
The distortion caused by an interactive fisheye lens can make it difficult for people to remember items and locations in the data space. In this paper we introduce the idea of vis...
Amy Skopik, Carl Gutwin