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ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
16 years 3 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 3 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
16 years 3 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
ICCAD
2006
IEEE
71views Hardware» more  ICCAD 2006»
16 years 3 months ago
Using CAD to shape experiments in molecular QCA
This paper examines how circuits and systems made from molecular QCA devices might function. Our design constraints are “chemically reasonable” in that we consider the charact...
Michael T. Niemier, Michael Crocker, Xiaobo Sharon...
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
16 years 3 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid