This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
Among the many stages of a simulation study, debugging a simulation model is the one that is hardly reported on but that may consume a considerable amount of time and effort. In t...
ProCom is a new component model for real-time and embedded systems, targeting the domains of vehicular and telecommunication systems. In this paper, we describe how the architectur...
Aneta Vulgarakis, Jagadish Suryadevara, Jan Carlso...
In this paper, we develop an automated framework for formal verification of timed continuous Petri nets (contPN). Specifically, we consider two problems: (1) given an initial set o...
Marius Kloetzer, Cristian Mahulea, Calin Belta, La...
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...