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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 10 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
IGIS
1994
118views GIS» more  IGIS 1994»
15 years 10 months ago
Surface Modelling with Guaranteed Consistency - An Object-Based Approach
There have been many interpolation methods developed over the years, each with their own problems. One of the biggest limitations in many applications is the non-correspondence of...
Christopher M. Gold, Thomas Roos
ASPLOS
1989
ACM
15 years 10 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
CF
2007
ACM
15 years 10 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 10 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
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