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DATE
2010
IEEE
105views Hardware» more  DATE 2010»
15 years 11 months ago
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs
Abstract—We present a set of modeling constructs accompanied by a high performance simulation kernel for accuracy adaptive transaction level models. In contrast to traditional, ï...
Rauf Salimi Khaligh, Martin Radetzki
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
15 years 11 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
APSEC
2002
IEEE
15 years 11 months ago
A Predictive Performance Model to Evaluate the Contention Cost in Application Servers
In multi-tier enterprise systems, application servers are key components to implement business logic and provide services. To support a large number of simultaneous accesses from ...
Shiping Chen, Ian Gorton
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
15 years 11 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DELTA
2002
IEEE
15 years 11 months ago
Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
Richard J. Blaikie, Maan M. Alkaisi, Steven M. Dur...
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