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VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 7 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 7 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
HPCA
2001
IEEE
16 years 7 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...
CHI
2004
ACM
16 years 7 months ago
Single-handed interaction techniques for multiple pressure-sensitive strips
We present a set of interaction techniques that make novel use of a small pressure-sensitive pad to allow one-handed direct control of a large number of parameters. The surface of...
Gábor Blaskó, Steven Feiner
POPL
2006
ACM
16 years 7 months ago
Formal certification of a compiler back-end or: programming a compiler with a proof assistant
This paper reports on the development and formal certification (proof of semantic preservation) of a compiler from Cminor (a Clike imperative language) to PowerPC assembly code, u...
Xavier Leroy
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