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PLDI
2004
ACM
16 years 8 days ago
Min-cut program decomposition for thread-level speculation
With billion-transistor chips on the horizon, single-chip multiprocessors (CMPs) are likely to become commodity components. Speculative CMPs use hardware to enforce dependence, al...
Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykuma...
VLDB
2004
ACM
245views Database» more  VLDB 2004»
16 years 5 days ago
A Multi-Purpose Implementation of Mandatory Access Control in Relational Database Management Systems
Mandatory Access Control (MAC) implementations in Relational Database Management Systems (RDBMS) have focused solely on Multilevel Security (MLS). MLS has posed a number of challe...
Walid Rjaibi, Paul Bird
PLDI
2010
ACM
15 years 12 months ago
Jinn: synthesizing dynamic bug detectors for foreign language interfaces
Programming language specifications mandate static and dynamic analyses to preclude syntactic and semantic errors. Although individual languages are usually well-specified, comp...
Byeongcheol Lee, Ben Wiedermann, Martin Hirzel, Ro...
230
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CODES
2009
IEEE
15 years 11 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 11 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...