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ICS
1999
Tsinghua U.
15 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
PPDP
1999
Springer
15 years 11 months ago
A Virtual Machine for a Process Calculus
Abstract. Despite extensive theoretical work on process-calculi, virtual machine specifications and implementations of actual computational models are still scarce. This paper pre...
Luís M. B. Lopes, Fernando M. A. Silva, Vas...
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 11 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
15 years 11 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
LCPC
1998
Springer
15 years 11 months ago
HPF-2 Support for Dynamic Sparse Computations
There is a class of sparse matrix computations, such as direct solvers of systems of linear equations, that change the fill-in (nonzero entries) of the coefficient matrix, and invo...
Rafael Asenjo, Oscar G. Plata, Juan Touriño...