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DSD
2006
IEEE
107views Hardware» more  DSD 2006»
16 years 20 days ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
16 years 17 days ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
HOTOS
2003
IEEE
15 years 12 months ago
Why Events Are a Bad Idea (for High-Concurrency Servers)
Event-based programming has been highly touted in recent years as the best way to write highly concurrent applications. Having worked on several of these systems, we now believe t...
J. Robert von Behren, Jeremy Condit, Eric A. Brewe...
PLDI
2003
ACM
15 years 12 months ago
Static array storage optimization in MATLAB
An adaptation of the classic register allocation algorithm to the problem of array storage optimization in MATLAB is presented. The method involves the decomposition of an interfe...
Pramod G. Joisha, Prithviraj Banerjee
SAC
2003
ACM
15 years 12 months ago
Validation of Code-Improving Transformations for Embedded Systems
Programmers of embedded systems often develop software in assembly code due to inadequate support from compilers and the need to meet critical speed and/or space constraints. Many...
Robert van Engelen, David B. Whalley, Xin Yuan