Sciweavers

36320 search results - page 703 / 7264
» From Code to Models
Sort
View
VTC
2008
IEEE
16 years 1 months ago
Construction of Regular Quasi-Cyclic Protograph LDPC codes based on Vandermonde Matrices
Abstract— In this contribution, we investigate the attainable performance of quasi-cyclic (QC) protograph Low-Density Parity-Check (LDPC) codes for transmission over both Additiv...
Nicholas Bonello, Sheng Chen, Lajos Hanzo
181
Voted
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
16 years 1 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
INFOCOM
2007
IEEE
16 years 1 months ago
On the Performance Analysis of Network-Coded Cooperation in Wireless Networks
—In this letter, a network-coded cooperation scheme with dynamic coding mechanism (DC-NCC) is proposed. In DCNCC, the relay dynamically adapts forming the network-coded data base...
Cong Peng, Qian Zhang, Ming Zhao 0001, Yan Yao
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
16 years 1 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
16 years 1 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba