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CODES
2006
IEEE
16 years 22 days ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu
LCTRTS
2004
Springer
16 years 1 days ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
SIGMETRICS
1996
ACM
174views Hardware» more  SIGMETRICS 1996»
15 years 10 months ago
Embra: Fast and Flexible Machine Simulation
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
Emmett Witchel, Mendel Rosenblum
CODES
2009
IEEE
16 years 1 months ago
Exploiting data-redundancy in reliability-aware networked embedded system design
This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach n...
Martin Lukasiewycz, Michael Glaß, Jürge...
ANSS
2008
IEEE
16 years 1 months ago
SCAR - Scattering, Concealing and Recovering Data within a DHT
This paper describes a secure and reliable method for storing data in a distributed hash table (DHT) leveraging the inherent properties of the DHT to provide a secure storage subs...
Bryan N. Mills, Taieb Znati