Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Proposed in this paper is the architecture of a PLC programming environment that enables a visual verification of PLC programs. The proposed architecture integrates a PLC program ...
Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeu...
Software modularization activities remain without the guidance of formal theories and models. According to Baldwin and Clark's [1] design rule theory (DRT) , modular architec...
Matthew J. LaMantia, Yuanfang Cai, Alan MacCormack...
This paper introduces a method for automatic composition of Semantic Web services using Linear Logic (LL) theorem proving. The method uses Semantic Web service language (DAML-S) f...