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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
SSDBM
2000
IEEE
155views Database» more  SSDBM 2000»
15 years 11 months ago
Knowledge-Based Integration of Neuroscience Data Sources
The need for information integration is paramount in many biological disciplines, because of the large heterogeneity in both the types of data involved and in the diversity of app...
Amarnath Gupta, Bertram Ludäscher, Maryann E....
DAC
1999
ACM
15 years 10 months ago
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
Vijay Sundararajan, Keshab K. Parhi
DAC
1994
ACM
15 years 10 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
DAC
2007
ACM
15 years 10 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley