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» Formal specification: a roadmap
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MEMOCODE
2010
IEEE
15 years 4 months ago
Monitoring temporal SystemC properties
Monitoring temporal SystemC properties is crucial for the validation of functional and transaction-level models, yet the current SystemC standard provides no support for temporal s...
Deian Tabakov, Moshe Y. Vardi
ICTAI
2009
IEEE
15 years 4 months ago
Merging Qualitative Constraint Networks in a Piecewise Fashion
We address the problem of merging qualitative constraints networks (QCNs). We point out a merging algorithm which computes a consistent QCN representing a global view of the input...
Jean-François Condotta, Souhila Kaci, Pierr...
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
16 years 6 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
SAFECOMP
1998
Springer
15 years 10 months ago
An Agenda for Specifying Software Components with Complex Data Models
Abstract. We present a method to specify software for a special kind of safetycritical embedded systems, where sensors deliver low-level values that must be abstracted and pre-proc...
Kirsten Winter, Thomas Santen, Maritta Heisel
TSE
2002
94views more  TSE 2002»
15 years 6 months ago
Behavior Protocols for Software Components
In this paper, we propose a means to enhance an architecture description language with a description of component behavior. A notation used for this purpose should be able to expr...
Frantisek Plasil, Stanislav Visnovsky