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FMCAD
1998
Springer
15 years 11 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
ICML
1996
IEEE
16 years 7 months ago
Discretizing Continuous Attributes While Learning Bayesian Networks
We introduce a method for learning Bayesian networks that handles the discretization of continuous variables as an integral part of the learning process. The main ingredient in th...
Moisés Goldszmidt, Nir Friedman
CSCWD
2009
Springer
16 years 1 months ago
Random stimulus generation with self-tuning
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
ISCIS
2009
Springer
16 years 1 months ago
Predicting future object states using learned affordances
Abstract—The notion of affordances was proposed by J.J. Gibson, to refer to the action possibilities offered to the organism by its environment. In a previous formalization, affo...
Emre Ugur, Erol Sahin, Erhan Oztop
KCAP
2003
ACM
16 years 1 days ago
FONTE: factorizing ONTology engineering complexity
Because it is difficult to engineer a complex ontology with time, we here consider a method that allows for factorizing the complexity of the engineering process, FONTE (Factoriz...
Jorge Santos, Steffen Staab