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DAC
2002
ACM
16 years 7 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
IWFM
1998
15 years 7 months ago
Formal Engineering of the Bitonic Sort using PVS
In this paper, we present a proof that the bitonic sort is sound using PVS, a powerful specification and verification environment. First, we briefly introduce this well-known para...
Raphaël Couturier
IFIP
2010
Springer
15 years 1 months ago
A Formal Analysis of Authentication in the TPM
The Trusted Platform Module (TPM) is a hardware chip designed to enable computers to achieve a greater level of security than is possible in software alone. To this end, the TPM pr...
Stéphanie Delaune, Steve Kremer, Mark Dermo...
CCS
2009
ACM
15 years 10 months ago
On voting machine design for verification and testability
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...
Cynthia Sturton, Susmit Jha, Sanjit A. Seshia, Dav...
ACSC
2004
IEEE
15 years 10 months ago
Automatic Derivation of Loop Termination Conditions to Support Verification
This paper introduces a repeatable and constructive approach to the analysis of loop progress and termination conditions in imperative programs. It is applicable to all loops for ...
Daniel Powell