714 search results - page 83 / 143 » Formal Verification of Cognitive Models |
153
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SIMUTOOLS
2008
15 years 7 months ago
2008
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
216
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DLT
2009
15 years 4 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
159
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ICFEM
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. CSP is a well-established formalism for modelling and verification of concurrent reactive systems based on refinement. Consolidated denotational models and an effective t...
177
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SIGSOFT
2007
ACM
16 years 6 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
161
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FMCAD
2006
Springer
15 years 9 months ago
2006
Springer
In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent yea...