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FTRTFT
1998
Springer
15 years 11 months ago
Fair Synchronous Transition Systems and Their Liveness Proofs
We present a compositional semantics of synchronous systems that captures both safety and progress properties of such systems. The fair synchronous transitions systems (fsts) mode...
Amir Pnueli, Natarajan Shankar, Eli Singerman
FMCAD
2004
Springer
15 years 10 months ago
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
Orna Grumberg, Assaf Schuster, Avi Yadgar
FMICS
2006
Springer
15 years 10 months ago
SAT-Based Verification of LTL Formulas
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
Wenhui Zhang
FORMATS
2006
Springer
15 years 10 months ago
A Dose of Timed Logic, in Guarded Measure
We consider interval measurement logic IML, a sublogic of Zhou and Hansen's interval logic, with measurement functions which provide real-valued measurement of some aspect of ...
Kamal Lodaya, Paritosh K. Pandya
SAS
2000
Springer
149views Formal Methods» more  SAS 2000»
15 years 10 months ago
FULLDOC: A Full Reporting Debugger for Optimized Code
As compilers increasingly rely on optimizations to achieve high performance, the effectiveness of source level debuggers for optimized code continues to falter. Even if values of s...
Clara Jaramillo, Rajiv Gupta, Mary Lou Soffa