Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
Claude Helmstetter, Florence Maraninchi, Laurent M...
Abstract. Symbolic state-space generators are notoriously hard to parallelise. However, the Saturation algorithm implemented in the SMART verification tool differs from other seque...
Behrmann et al. posed the question whether "To Store or Not To Store" [1] states during reachability analysis, in order to counter the effects of the well-known state spa...
Abstract. We present experiences from a case study where a model-based approach to black-box testing is applied to verify that a Wireless Application Protocol (WAP) gateway conform...
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...