4036 search results - page 351 / 808 » Formal Methods |
161
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FMCAD
2009
Springer
16 years 1 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
130
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FMCAD
2009
Springer
16 years 1 months ago
2009
Springer
—Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades...
172
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MEMOCODE
2008
IEEE
16 years 1 months ago
2008
IEEE
—Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system’...
211
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MEMOCODE
2008
IEEE
16 years 1 months ago
2008
IEEE
Equivalence checking is a classical verification method determining if a finite-state concurrent system (protocol) satisfies its desired external behaviour (service) by compari...
169
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FMCO
2007
Springer
16 years 27 days ago
2007
Springer
This paper describes the architecture of costa, an abstract interpretation based cost and termination analyzer for Java bytecode. The system receives as input a bytecode program, (...