This paper presents results on processor specification from a specialized high-level finite state machine (FSM) language. The language is an extension and enhancement of earlier...
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyu...
Timed automata (TA) are a widely used model for real-time systems. Several tools are dedicated to this model, and they mostly implement a forward analysis for checking reachability...
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into...
We present a calculus which can transfer specifications to objects for the development of real-time systems. The object model is based on a practical OO development technique--HRT...
Zhiqiang Chen, Antonio Cau, Hussein Zedan, Xiaodon...